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1 ? fn9119.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2003, 2004, 2005, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6131, isl6132 multiple voltage supervisory ics the isl6131 and isl6132 are a family of high accuracy multi voltage supervisory ics designed to monitor voltages greater than 0.7v in applications ranging from microprocessors to indust rial power systems. the isl6131 is an undervoltage four supply supervisor whereas the isl6132 is a two voltage supervisor monitoring both for undervoltage (uv) and overvoltage (ov) conditions. both ics feature four external resistor programmable voltage monitoring (vmon) inputs each with a related status output that individually reports the related monitor input condition. in addition there is a pgood (power good) signal that asserts high when the status outputs are in their correct state. there is a stab ility delay of approximately 160ms to ensure that the moni tored supply is stable before status and pgood are released to go high. the pgood and status outputs are open-drain to allow oring of the signals and interfacing to a wide range of logic levels. status and pgood outputs are guaranteed to be valid with ic bias lower than 1v eliminating concern about status and pgood outputs during ic bias up and down. vmon inputs are designed to ignore momentary transients on the monitored supplies. features ? operates from 1.5v to 5.5v supply voltage ? four adjustable voltage monitoring thresholds ? 150ms status/pgood stability time delay ? four individual open drain status outputs ? guaranteed status/pgood valid to v dd <1v ?v dd and vmon glitch immunity ?v dd lock out ? 4mm x 4mm qfn package ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free (rohs compliant) applications ? multivoltage dsps and processors ? p voltage monitoring ? embedded control systems ? graphics cards ? intelligent instruments ? medical equipment ? network routers ? portable battery-powered equipment ? set-top boxes ? telecommunications systems ordering information part number part marking temp. range (c) package pkg. dwg. # isl6131irza* (note) 61 31irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl6132irza* (note) 61 32irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 ISL613XSUPEREVAL2 evaluation platform *add ?-t? suffix for tape and reel. pleas e refer to tb347 for details on reel specifications. note: these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet august 17, 2010
2 fn9119.4 august 17, 2010 figure 1. isl6131 typical application usag e figure 2. isl6132 typical application usage status d status c status b status a vmon_b vmon_a vmon_d vmon_c a in ground v dd b in c in d in pgood en uvstatus_1 ovstatus_1 uvstatus_2 ovstatus_2 uvmon_2 uvmon_1 ovmon_2 ovmon_1 v1 in ground v dd v2 in pgood1 en1 pgood2 en2 ru rm rl isl6131, isl6132
3 fn9119.4 august 17, 2010 pinout isl6131, isl6132 (24 ld qfn) top view 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 pd pin descriptions pin pin name function description 6131 6132 23 23 v dd bias ic from nominal 1.5v to 5v 10 10 gnd ic ground 20 na vmon_a on the isl6131 these inputs provide for a programmable uv th reshold referenced to an internal 0.633v. the related status output will assert once the related input > internal reference voltage. on the isl6132, these inputs provide for a programmable uv and ov threshold referenced to an internal 0.633v reference. in the ?ab? pair vmon_a is the uv input and vmon_b is the ov input. in the ?cd? pair vmon_c is the uv input and vmon_d is the ov input. these inputs have a 30 s glitch filter to prevent pgood reset due to a transient. 12 na vmon_b 17 na vmon_c 14 na vmon_d na 12 ovmon_1 na 20 uvmon_1 na 17 uvmon_2 na 14 ovmon_2 24 24 pgood on the isl6131 , pgood is the boolean and functi on of all four status outputs. on the isl6132, pgood is for the ab pair and signals high when the monitored voltage is within the specified window and the a and b status output states are correct. this is an open drain output and is to be pulled high to the appropriate level with an external resistor to a v dd maximum level. na 9 pgood2 pgood2 is for the cd pair and signals high when the monitored voltage is within the specified window and when the c and d status output states are correct. this is an open drain output and is to be pulled high to the appropriate level with an external resistor to a v dd maximum level. 2nastatus_aon the isl6131 each status provides a high signal through pull-up resistors about 160ms after its related vmon has continuously been > vuv_vth. this delay is for stabilization of monitored voltages. status will de- assert and pull low upon vmon not being satisfied for about 30 s. on the i sl6132 the status outputs indicate compliance with a high output state for each pair of monitors. 5nastatus_b 6nastatus_c 7nastatus_d na 5 ovstatus_1 na 2 uvstatus_1 na 6 uvstatus_2 na 7 ovstatus_2 11 en1 on isl6131 provides 4 voltage uv function enabling/di sabling input. internally pulled up to v dd . controls monitor 1 (ab pair) on isl6132. na 11 en2 on isl6132 , controls monitor 2 (cd pair) voltage, voltag e monitoring function enabling input, pulled up to v dd . - - pd thermal pad. should be electrically connected to gnd. nc 3, 4, 8, 13, 15, 16, 18, 19, 21, 22 no connect isl6131, isl6132
4 fn9119.4 august 17, 2010 absolute maximum rati ngs thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v vmon, enable, status, pgood . . . . . . . . . . -0.3v to v dd +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv (hbm) operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . . +1.5v to +5.5v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 4x4 qfn package . . . . . . . . . . . . . . . . 48 9 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. all voltages are relative to gnd, unless otherwise specified. electrical specifications nominal v dd = 1.5v to +5v, t a = t j = -40c - 85c, unless otherwise specified parameter symbol test conditions min (note 4) typ max (note 4) unit vmon/enable inputs vmon threshold v vmonvth t j = +25c 619 633 647 mv vmon threshold temp. coeff. tc vmonvth t j from -40c to +85c - 40 - nv/c vmon hysteresis v vmonhys -10-mv vmon glitch filter tfil - 30 - s vmon minimum input impedance zin_min tj = +40c, vmon within 63mv of v vmonvth 8m enable l2h, delay to status & pgood vmon valid, en high to status & pg high - 160 - ms en h2l, delay to pgood en low to pgood low - - 0.1 s en h2l, delay to status en low to status low - 13 - s enable pull-up voltage en open - v dd -v enable threshold voltage v envth -v dd /2 - v status/pgood outputs status pull-down current i rst pd rst = 0.1v - 88 - ma status/pgood delay after vmon valid t delst vmon > v uvvth to status = 0.2v - 160 - ms status/pgood output low vol measured at v dd = 1.0v - 0.04 0.1 v bias ic supply current i vdd_5.5v v dd = 5v - 170 - a ic supply current i vdd_3.3v v dd = 3.3v - 145 - a ic supply current i vdd_1.5v v dd = 1.5v - 100 - a v dd power on v dd _por v dd high to low - 0.89 1 v v dd power on lock out v dd _lo v dd low to high - 0.91 - v note: 4. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. isl6131, isl6132
5 fn9119.4 august 17, 2010 description and operation the isl6131 is a four voltage high accuracy supervisory ic designed to monitor multiple voltages greater than 0.7v relative to pin 10 of the ic. upon v dd bias power up, the status and pgood outputs are held correctly low once v dd is as low as 1v. once biased to 1.5v the ic continuously monitors from one to four voltages independently through external resistor dividers comparing each voltage monitoring (vmon) pin voltage to an internal 0.633v (v vmonvth ) reference. with the en input driven high or open as each vmon input rises above v vmonvth a timer is set to ensure ~160ms of continuous compliance then t he related status output is released to be pulled high. the status outputs are open- drain to allow oring of these signals and interfacing to a logic high level up to v dd . the status are designed to reject short transients (~30 s) on the vmon inputs. once all status outputs are high a power good (pgood) output signal is generated high to indicate all the monitored voltages are greater than minimum compliance level. once any vmon input falls below v vmonvth for longer than the glitch filter ti me both the pgood and the related status output are pulled low. the other status outputs will remain high as long as their corresponding vmon voltage remains valid and the pgood validation process is reset. figure 1 illustrates isl6131 typical application schematic and figure 3 is an operational timing diagram. see figures 10 to 17 for isl6131 function and performanc e. figures 10 and 11 show the v dd rising along with status and pgood response. figures 12 and 13 illustrate vmon falling below v vmonvth and figure 14 illustrates vmon rising above v vmonvth with status and pgood response. figure 15 shows the v dd failing with status and pgood response. figures 16 and 17 illustrate enable to status and pgood timing. if less than four voltages are being monitored, connect the unused vmon pins to v dd for proper operation. all unused status outputs can be left open. the isl6132 is a dual voltage monitor for under and overvoltage compliance. figure 2 illustrates the typical isl6132 implementation schematic and figure 4 is the operational timing diagram. there are 2 pairs of monitors each with an undervoltage (uvmon) input and overvoltage (ovmon) input along with with associated status and pgood outputs. upon v dd bias power up, the status and pgood outputs are held correctly low once v dd is as low as 1v. once biased to 1.5v the ic continuously monitors the voltage through external resistor dividers comparing each vmon pin voltage to an internal 0.633v reference. at proper bias the ovstatus are pulled high and the uvstatus and pgood are pulled low. once the uvmon input > the vmon vth continuously for ~160 ms, its associated status output will release high indicating that the minimum voltage condition has been met. as both uvmon and ovmon inputs are satisfied the pgood output is released to go high indicating that the monitored voltage is within the specified window. figure 18 illustrates this performance for a 4v to 5v window. when vmon does not satisfy its voltage high or low criteria for more than the g litch filter time, the associated status and pgood are pulled low. figures 19 and 20 illustrate this performance for a 4v to 5v compliant window. figures 21-23 illustrate the vmon glitch filter timing to status and pgood notification and transient immunity. the enable input when pulled low allows for monitoring and reporting function to be disabled. figure 24 shows enable high to pgood timing for compliant voltage. when choosing resistors for the divider remember to keep the current through the st ring bounded by power loss tolerance at the top end and no ise immunity at the bottom end. for most applications total divider resistance in the 10k -100k range is advisable with 1% tolerance resistors being used to reduce monitoring error. referencing figures 1 and 2, choosing the two resistor values is straightforward for the isl6131 as the ratio of resistance should equal the ratio of the desired trip voltage to the internal reference, 0.633v). for the isl6131, two dividers of two resistors each can be employed to monitor the ov and uv levels for each voltage. otherwise, use a single three resistor string for each voltage. in the three resistor divider string the ratio of the desired over voltage trip point to the internal reference is equal to the ratio of the two upper resistors to the lowest (gnd connected) resistor. the desired under voltage trip point ratio to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. an example follows; 1. establish lower and upper trip level: 3.3v 20% or 2.64v (uv) and 3.96v (ov) 2. establish total resistor string value: 10k , ir = divider current 3. (rm+rl)*ir = 0.623v @ uv and rl * ir = 0.633v @ ov 4. rm+rl = 0.623v / ir @ uv => rm+rl = 0.623v / (2.64v /10k ) = 2.359k 5. rl = 0.633v / ir @ ov => rl = 0.633v /(3.96v/10k ) = 1.598k 6. rm = 2.359k - 1.598k = 0.761k 7. ru = 10k - 2.397k = 7.641k 8. choose standard value resistors that most closely approximate these ideal values. choosing a different total divider resistance value may yield a more ideal ratio with available resistors values . isl6131, isl6132
6 fn9119.4 august 17, 2010 typical performance curves figure 5. uv threshold figure 6. v dd current figure 3. isl6131 operational diagram bcd a vmonvth stsdly stsdly stsdly stsdly c vmon status outputs abcd pgood output c >tfil stsdly input voltage d 7 fn9119.4 august 17, 2010 applications usage using the ISL613XSUPEREVAL2 platform the ISL613XSUPEREVAL2 platform is the primary evaluation board for this family of supervisors and is designed to support the isl6131, isl6132. in addition, it also supports the isl6125 sequencer as it has open drain reset# outputs similar to th e status outputs of the isl6131 and isl6132 . the ISL613XSUPEREVAL2 is shipped with a isl6125 soldered into the smd channel 2 position and with 2 each of the isl6131 (1 socketed) and isl6132 loose packed. the four resistor divider strings are set so that vmon = vmon vth (0.633v) once supplies are 2.10v on the in_d, 1.27v on in_c, 4.27v on in_b and 2.78v on in_a. on the isl6131 these are the 4 uv levels at ~85% of 2.5v, 1.5v, 5v and 3.3v respectively. leds turned off are the pgood high indicators with d4 being the isl6131 indicator. with v dd ranging from 1.5v to 5v or shorted to in_a through jp1 and with an isl6131 in the socket, pgood will release to be pulled high once those minimum conditions are met. see figures 10 to 17 for performance and function examples. with the isl6132 in the socket and in_c and in_d tied to a common supply and in_a and in_b tied to a second supply the isl6132 will look for a voltage between 1.27v to 2.10v on the cd pair and between 2.78v and 4.27v for the ab pair. once either supply meets its requirement the related pgood will release to pull high and turn off the related led. see figures 18 to 24 for performance and function examples. figures 25 and 26 illustrate the ISL613XSUPEREVAL2 platform in image and schematic. using the isl6131, isl6132 for negative voltage monitoring applications the isl6131, isl6132 can be used for -v monitoring as it monitors any voltage more positi ve relative to its gnd pin. with correct bias differential these parts can monitor any voltage regardless of polarity or amplitude. using the isl6131 for ?loss less? sequencing applications the isl6131 can be used in a ?loss less? sequencing application where a monitored output voltage determines the start of the next sequenced turn-on. as shown in figure 7, vmon_a input looks at the common vin of several dc-dc converters and enables dc-dc_a with status _a, once both vin and enable are satisfied. vmon_b monitors the output of dc-dc_a and when the acceptable output voltage is reached, dc-dc_b is enabled with status_b output. this sequencing pattern is continued until all dc-dc outputs are on, at which time pgood signal will be released to indicate. 160ms delay from vmon > v vmonvth to status high ensures stability at each step prior to subsequent turn- on. additional isl6131s can be employed in parallel to sequence any number of dc-dc convertors is in this fashion. using the isl6131 for system voltage and over temperature monitoring being a multivoltage monitoring ic the isl6131 can also be used to monitor over temperature as well as voltage for a more complete coverage of syst em health. usi ng a negative temperature coefficient (ntc) passive device in place of one of the resistors in a vmon divider provides over temperature monitoring either locally or remotely. evaluations of this application configuration have involved the qt0805t-202j, qt0805y-502j and qt0805y-103j ntcs from quality thermistor. isl6131 over temperature monitoring is not as accurate as specific temperature monitor ics but this implementation provides a cost efficient solution with 5% tolerances achievable. see figures 8 - 9 for over te mp sensing configuration and operation results. in this example, the desired maximum temp is 100c. the qt0805y-103j ntc was placed at the end of 3 feet of twis ted pair wire to emulate a remote sensing application. from the quality thermistor data sheet, this ntc device has a +25c value of 10k and at +100c a value of 0.923k. an accompanying standard value resistor of 3.83k was chosen for divide r so that at 100c, vmon ~0.633v with the bias voltage at 3.3v. figure 7. isl6131 ?lossless? sequencing configuration dc-dc_a vin vout en vin vin vout vout en en dc-dc_b dc-dc_c vmon_a vmon_d vmon_c vmon_b abc status pgood gnd vdd enable isl6131 isl6131, isl6132
8 fn9119.4 august 17, 2010 the resulting falling vmon tr ip point with configuration shown is ~0.634v, with ~0.642v for rising which equates to ~95c for under temperature and ~97c for over temperature respectively. choosing the standard resistor value above and below r1 allows for small adjustments in the temperature trip point. the low isl6131 vmon temperature coefficient makes this a viable and low cost addition to complete system monitoring. figure 8. isl6131 over temp sensing configuration vdd vmon gnd t 3.3v 3.83k qt0805y-103j isl6131 (remote heat source location) status temp indicator r1 figure 9. isl6132 over temp sensing result temp (c) vmon (v) temp status 25 2.36 h = under temp 50 1.61 h = under temp 75 1.01 h = under temp 95 0.67 h = under temp 100 0.61 l = over temp 105 0.54 l = over temp temp status 5v/div 10s/div vmon 0.1v/div low = over temp functional and performance waveforms figure 10. isl6131 v dd rising figure 11. isl6131 v dd rising with pull-up 1v/div 100 s/div v dd rising status outputs to v dd pgood 1v/div 200 s/div status outputs pulled-up to 1.5v v dd rising pgood isl6131, isl6132
9 fn9119.4 august 17, 2010 figure 12. isl6131 vmon falling to pgood figure 13. isl6131 vmon falling to pgood figure 14. isl6131 uv rising to pgood figure 15. isl6131 v dd falling figure 16. isl6131 enable l2h to pgood figure 17. isl6131 en h2l to pgood functional and performance waveforms (continued) 1v/div 40ms/div vmon falling below uv vth (0.1v/div) related status output unrelated status outputs pgood uv vth 0.63v 1v/div 10ms/div vmon falling below uv vth (0.1v/div) related status output unrelated status outputs pgood uv vth 0.63v 1v/div 20ms/div vmon rising above uv vth (0.1v/div) related status output unrelated status outputs pgood uv vth 0.63v 1v/div 40ms/div v dd falling status outputs pgood 2v/div 20ms/div pgood enable status 2v/div 2s/div pgood enable status isl6131, isl6132
10 fn9119.4 august 17, 2010 figure 18. isl6132 turn-on figure 19. isl6132 in uv condition figure 20. isl6132 in ov condition figure 21. isl6132 uv glitch filter timing figure 22. isl6132 ov glitch filter timing figure 23. isl6132 glitch filter transient immunity functional and performance waveforms (continued) 1v/div 40ms/div v dd rising ov status rising uv/pgood status rising monitoring 4v to 5v 1v/div 10ms/div monitoring 4v to 5v monitored voltage falling pgood and uv status pulled low ov status 1v/div 10ms/div monitoring 4v to 5v monitored voltage rising pgood and ov status pulled low uv status 5v/div 10s/div vmon falling (1v/div) 4v min limit uv status ov status pgood monitoring 4v to 5v 5v/div 10s/div vmon rising (1v/div) 5v max limit uv status ov status pgood monitoring 4v to 5v 8s/div vmon 5.5v to 3.5v uv, ov status & pgood 5v out isl6131, isl6132
11 fn9119.4 august 17, 2010 figure 24. isl6132 enable to pgood functional and performance waveforms (continued) 20ms/div enable 1v/div pgood ov, uv status figure 25. ISL613XSUPEREVAL2 photograph isl6131, isl6132
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9119.4 august 17, 2010 figure 26. ISL613XSUPEREVAL2 channel 1 schematic status r1 r2 r3 r4 r5 r6 r7 r8 c1 gnd vmon2 (ov1) vmon4 (ov2) vmon3 (uv2) vmon1 (uv1) 12 3 4 v dd pgood1 r15 r16 r18 r17 pgood2 in2 in4 in3 in1 jp1 r10 d4 d3 r9 en1 en2 isl6131, isl6132 v dd table 1. isl6131supereval2 board channel 1 component listing component designator component function component description dut1 isl6131 , quad under voltage supervisor in socket intersil, isl6131ir quad under voltage supervisor dut2 isl6132 , dual over & under voltage supervisor in bag intersil, isl6132ir dual over & under voltage supervisor r1a in2 to vmonb (ov1) resistor for divider string 8.45k 1%, 0402 r2a vmonb (ov1) to gnd resist or for divider string 1.47k 1%, 0402 r7a in1 to vmona (uv1) resistor for divider string 7.68k 1%, 0402 r8a vmona (uv1) to gnd resistor for divider string 2.26k 1%, 0402 r3a in4 to vmond (ov2) resistor for divider string 6.98k 1%, 0402 r4a vmond (ov2) to gnd resistor for divider string 3.01k 1%, 0402 r5a in3 to vmonc (uv2) resistor for divider string 4.99k 1%, 0402 r6a vmonc (uv2) to gnd resistor for divider string 4.99k 1%, 0402 r15-r18 status pull-up resistors 5.1k 10%, 0402 c1a decoupling capacitor 0.1 f, 0805 d3, d4 pgood# indicator smd red led isl6131, isl6132
13 fn9119.4 august 17, 2010 isl6131, isl6132 package outline drawing l24.4x4 24 lead quad flat no-lead plastic package rev 4, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 10 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 10 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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